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Write a VHDL entity and architecture that perform the following:
1) Divide your two ID numbers into four 2-digit numbers
2) Add each 2-digit numbers from the first ID number with the corresponding 2-digit number of the second ID number. The output of this step should be four 3-digit numbers.
3) Pad the four 3-digit numbers into one 12-digit number. This is the output of the VHDL code.
4) Write a VHDL testbench to test your code, and simulate it.
Example:
1) First ID: 12345678 è 12, 34, 56, 78
Second ID: 97654310 è 97, 65, 43, 10
2) 12+97=109; 34+65=099; 56+43=099; 78+10=088
3) output = 109099099088

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